`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:49:55 10/22/2012 
// Design Name: 
// Module Name:    MUL_SUM_UNIT 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MUL_SUM_UNIT #(parameter LOG_CYCLE = 8, CYCLE=256, WIDTH = 16)
(
    input clk,
    input rst,
	 input signed [WIDTH-1:0] a_r,
    input signed [WIDTH-1:0] a_i,
    input signed [WIDTH-1:0] b_r,
    input signed [WIDTH-1:0] b_i,
    output signed [WIDTH+WIDTH+1+LOG_CYCLE-1:0] out_r,
    output signed [WIDTH+WIDTH+1+LOG_CYCLE-1:0] out_i
    );


	wire signed[WIDTH+WIDTH+1-1:0] cplx_mul_out_r;
	wire signed[WIDTH+WIDTH+1-1:0] cplx_mul_out_i;


	CPLX_MUL_UNIT #(WIDTH) U_cplx_mul 
	(
		.clk(clk), 
		.rst(rst), 
		.a_r(a_r), 
		.a_i(a_i), 
		.b_r(b_r), 
		.b_i(b_i),
		.out_r(cplx_mul_out_r), 
		.out_i(cplx_mul_out_i)	
	);
	
	ACC_UNIT #(LOG_CYCLE, CYCLE, WIDTH+WIDTH+1) U_acc 
	(
		.clk(clk), 
		.rst(rst), 
		.a_r(cplx_mul_out_r), 
		.a_i(cplx_mul_out_i),
		.out_r(out_r), 
		.out_i(out_i)
	);

		
endmodule